1. Field of the Invention
The present invention relates to a video display apparatus, and more specifically to a video display apparatus having a phase-locked loop used for bringing a horizontal scan signal frequency used in a television receiver and a personal computer display, into synchronism with a synchronizing input signal frequency. In this specification, "phase-locked loop" will be abbreviated to "PLL".
2. Description of Related Art
In video display apparatus of this type, for example, in a television receiver monitor, a horizontal scan signal for a display is generated in synchronism with a horizontal synchronous signal which is separated from an input composite video signal by a synchronous signal separation circuit. Since it is not preferred that the horizontal scan signal is influenced by noises and others included in the horizontal synchronous signal, a PLL circuit is generally used in order to eliminate the disturbance as mentioned above and in order to ensure a stable horizontal synchronous signal frequency.
As well known, the PLL circuit includes a voltage or current controlled oscillator and a phase comparator having an output connected to a low pass filter (LPF). The phase comparator compares an output of the oscillator with a leading edge or a center of a synchronous pulse which is reference signal. An error voltage or current indicative of the result of the comparison, is integrated by the low pass filter, and supplied as a control voltage or current to the oscillator, to change the phase and the frequency of the oscillator until the output frequency of the oscillator is brought into phase with the synchronous pulse.
Referring to FIG. 1, there is shown, in a block diagram form, one prior art video display apparatus using the PLL circuit, which was disclosed in Japanese Patent Application Pre-examination Publication No. JP-A-62-159980 corresponding to U.S. Pat. No 4,634,939, the content of which is incorporated by reference in its entirety into this application.
The shown prior art video display apparatus includes a PLL circuit 1 generating an oscillation signal VF following the frequency of an input horizontal synchronous signal HI, a tracking circuit 2 for outputting a tracking control signal IF for moving the oscillation frequency into a predetermined capture range at the time of an abrupt change of the frequency of the synchronous signal HI, as when the synchronous signal HI is switched over, and for maintaining the oscillation frequency when no synchronous signal HI is supplied, and an output circuit 2 receiving the oscillation signal VF to amplify the oscillation signal VF to a predetermined output level and to output the amplified signal as a horizontal output signal HO.
The PLL circuit 1 includes a waveform shaper 11 receiving the horizontal synchronous signal HI to output a horizontal synchronous pulse H having a constant pulse width, a phase detector 12 for detecting a phase difference between the horizontal synchronous pulse H and the oscillation signal VF, to output a phase difference signal P1, a low pass filter 13 for integrating the phase difference signal P1 to convert the phase difference signal P1 into a current signal F1, a current adder 14 for adding the current signal F1 and the tracking control signal IF, which is also a current signal, to generate a control signal C, and a current controlled oscillator 15 responding to the control signal C to oscillate the oscillation signal VF.
The tracking circuit 2 includes a frequency-to-voltage converter 21 receiving the horizontal synchronous pulse H to convert the frequency of the horizontal synchronous pulse H into a voltage signal VH, a low pass filter 22 for integrating the voltage signal VH to output an integration signal F2, a voltage supply 23 for outputting a voltage signal FL which causes the oscillator 15 to oscilliate at a minimum free running frequency, a clipping diode 24, and a voltage-to-current converter 25 for converting the voltage of the signals F2+FL into the tracking control signal IF which is a current signal.
The output circuit 3 comprises a phase shifter 31 responding to a control signal F3 to phase-shift the oscillation signal VF and to output a phase-shifted signal PS, an output amplifier 32 responding to the phase-shifted signal PS to output a horizontal deflection output signal HO and a blanking pulse PB, a phase detector 33 for detecting a phase difference between the blanking pulse PB and the oscillation signal VF to generate a phase difference signal P2, and a low pass filter 34 for integrating the phase difference signal P2 to generate the control signal F3.
Now, an operation of the prior art video display apparatus will be described with FIG. 1 and FIG. 2 which is a timing chart illustrating waveforms of various signals in the circuit shown in FIG. 1.
First, when the PLL circuit 1 is in a locked condition, namely when the frequency of the horizontal synchronous pulse H is substantially coincident with the frequency of the oscillation signal VF, the waveform shaper 11 of the PLL circuit 1 shapes the received input horizontal synchronous signal HI to output the horizontal synchronous pulse H having a constant pulse width, which is supplied to the phase detector 12 and the frequency-to-voltage converter 21. The phase detector 12 compares the phase of the horizontal synchronous pulse H and the phase of the oscillation signal VF which is the output of the PLL circuit 1, and outputs the phase difference signal P1. The low pass filter 13 integrates the phase difference signal P1 and outputs the current signal F1. In the above mentioned locked condition, the tracking control signal IF is at a constant value, and therefore, the current adder 14 adds the tracking control signal IF of the constant value and the current signal F1, to generate the control signal C. The current controlled oscillator 15 oscillates and generates the oscillation signal VF having the frequency corresponding to the current value of the control signal C. This oscillation signal VF is supplied to the phase detector 12 and the phase shifter 31 and the phase detector 33 of the output circuit 3. Thus, the PLL circuit 1 operates to the effect that the phase difference signal P1 outputted from the phase detector 12 becomes zero, namely, the frequency of the oscillation signal VF generated by the current controlled oscillator 5 becomes coincident with the frequency of the horizontal synchronous signal HI.
On the other hand, the frequency-to-voltage converter 21 of the tracing circuit 2 converts the frequency of the received horizontal synchronous pulse H into the voltage signal VH, which is supplied to the low pass filter 22. The low pass filter 22 eliminates a high frequency component such as noises and others, included in the voltage signal VH, and integrates the voltage signal VH to generate the integration signal F2 to the voltage-to-current converter 25. The voltage-to-current converter 25 converts the integration signal F2 into a current value and generates the tracking control signal IF having the current value in proportion to the frequency of the horizontal synchronous pulse H.
The minimum oscillation frequency voltage supply 23 generates the minimum voltage signal FL for setting the frequency of the current controlled oscillator 15 to a constant value, in this case, to a minimum value which is equal to or lower than a lower frequency of a normal operation, when no horizontal synchronous pulse H is supplied. The minimum voltage signal FL is supplied through the clipping diode 24 to the voltage-to-current converter 25.
Here, when the PLL circuit 1 is unlocked to be brought into an unlocked condition because of a frequency change of the input horizontal synchronous signal H1 or another reason, the tracking circuit 2 generates the tracking control signal IF in proportion to the frequency of the horizontal synchronous pulse H. The tracking control signal IF is supplied to the current adder 14. In the unlocked condition, since the phase difference signal P1, namely, the integration signal F1, is almost zero, the current adder 14 outputs the tracking control signal IF as it is, as the control signal C to the current controlled oscillator 15. Accordingly, the current controlled oscillator 15 operates in an open loop control mode of setting the oscillation frequency under control of the tracking control signal IF, and generates the oscillation signal VF. If the oscillation signal VF becomes almost the frequency of the horizontal synchronous pulse H and enters in the capture range of the PLL circuit 1, the PLL circuit 1 is put in the locked condition as mentioned above.
Alternatively, when the input horizontal synchronous signal H1 is not supplied, namely, when no horizontal synchronous pulse H is supplied from the waveform shaper 2, the integration signal F2 becomes zero, so that the diode 24 becomes conductive, and therefore, the voltage signal FL generated in the voltage supply 23 is supplied through the diode 24 to the voltage-to-current converter 25. Thus, the voltage-to-current converter 25 outputs the tracking control signal IF corresponding to the voltage signal FL. Accordingly, the current controlled oscillator 15 operates in a free running oscillation in an open loop control mode of setting the oscillation frequency under control of the tracking control signal IF corresponding to the voltage signal FL, and generates the oscillation signal VF of the minimum oscillation frequency.
The phase detector 33 in the output circuit 3 detects a phase difference between the oscillation signal VF and the blanking pulse PB outputted from the output amplifier 32, to output the phase difference signal P2. The low pass filter 34 integrates the phase difference signal P2 to output the control signal F3. The phase shifter 31 is controlled by the control signal F3 to shift the phase of the oscillation signal VF supplied from the PLL circuit 1, by a constant amount, and to output the phase-shifted signal PS to the output amplifier 32. This output amplifier 32 outputs the horizontal output signal HO which is a deflecting current signal for a deflecting coil (not shown), so that a cathode ray tube (CRT) which is a display means, is horizontally scanned. Furthermore, the output amplifier 32 outputs the blanking pulse PB which is obtained by delaying the horizontal output signal HO by a predetermined period and which corresponds to a blanking period in the horizontal scanning. The blanking pulse PB is supplied to the phase detector 33.
In the prior art video display apparatus mentioned above, the tracking circuit 2 performs the frequency tracking control of the current controlled oscillator 15 by the tracking control signal which is generated by frequency-to-voltage-converting the horizontal synchronous pulse H having the constant pulse width obtained by use of the waveform shaper 11. On the other hand, in the composite video signal to be displayed, no horizontal synchronous signal does not exist during a period of a vertical synchronous signal. Therefore, during the vertical synchronous signal period (namely, the blanking period) and just after the vertical synchronous signal period, the frequency-to-voltage-conversion is carried out in a condition in which no horizontal synchronous signal exists. Accordingly, during the vertical synchronous signal period, there occurs a frequency conversion error which causes the value of the voltage signal VH to become lower than the value in a horizontal synchronous signal period. As a result, the tracking control signal IF changes, with the result that the oscillation signal VF also changes, and an image distortion due to a phase deviation occurs in an upper portion of a display screen which corresponds to a period just after the blanking period. As a countermeasure, the frequency conversion error in the blanking period is suppressed by integrating the voltage signal VH by the low pass filter 22 constructed to include a large capacitance capacitor and therefore to have a large time constant.
However, if the low pass filter 22 is constructed to include a large capacitance capacitor and therefore to have a large time constant in order to prevent the image distortion attributable to missing of the horizontal synchronous signal in the blanking period, a frequency change tracking capability becomes low when the frequency of the horizontal synchronous signal is changed. As a result, in a certain period just after the change of the horizontal synchronous signal frequency, a horizontal size varies in the display screen.
Furthermore, when the horizontal synchronous signal is not supplied, the free running oscillation frequency is set by the constant voltage supplied through the clipping diode to the output side of the low pass filter of the tracking circuit. Here, this constant voltage is required to be set lower than the voltage of the integration signal which is outputted from the low pass filter and which corresponds to the lowest frequency in the normal operation, in order to prevent the constant voltage from reversely flowing. Accordingly, it is a matter of course that the free running oscillation frequency is not greater than the lowest frequency mentioned above.